1. Field of the Invention
The present invention relates to a memory IC and a memory device and, more particularly, to a memory IC whose memory capacity can be easily expanded and to a memory device whose memory capacity is expanded by connecting a plurality of such memory ICs to it.
2. Description of the Related Art
FIG. 6 shows a conventional memory IC. An address bus 2 composed of address input lines A.sub.1 to A.sub.n used for addressing purposes, and a data bus 6 composed of data input/output lines D.sub.1 to D.sub.m are connected to a static RAM 1. A write enable line 3 is connected to a write enable input terminal WE of the static RAM 1; a read enable line 4 is connected to a read enable input terminal OE; and a chip select input line 5 is connected to a chip select input terminal S.
When a low-level chip select signal is input through the chip select input line 5, data on the data bus 6 is written into an address specified by the address bus 2 or data which is stored at an address specified by the address bus 2 is supplied to the data bus 6. This writing is based on a low-level write enable signal transmitted through the write enable line 3, and the reading is based on a low-level read enable signal transmitted through the read enable line 4.
FIG. 7 shows the structure of a memory device whose capacity is expanded by employing a plurality of such memory ICs. Address input lines A.sub.1 to A.sub.n of an address bus 20, a write enable line 3, a read enable line 4 and a data bus 6 are each connected to all static RAMs 11 to 14, which are of the same type as that of the static RAM 1 shown in FIG. 6. A decoder 21 is connected to a chip select input terminal S of each of the static RAMs 11 to 14. Address input lines A.sub.n+1 and A.sub.n+2 from among the address input lines of the address bus 20 are connected to input terminals P1 and P2 of the decoder 21, respectively. A chip enable signal line 22 is connected to a chip enable input terminal CE. Output terminals T1 to T4 of the decoder 21 are connected to chip select input terminals S of the static RAMs 11 to 14, respectively.
Table 1 shows the functions of the decoder 21.
TABLE 1 ______________________________________ Input Output An + 1 An + 2 CE Tl T2 T3 T4 ______________________________________ X X H H H H H L L L L H H H H L L H L H H L H L H H L H H H L H H H L ______________________________________
where "X" denotes that signals may be at either a high or a low level.
There are several operational modes of the static RAMs 11 to 14, such as a write mode, a read mode and a standby mode. A description will now be given of the operation of the memory device shown in FIG. 7 when it is in the write mode.
When data is written into the first static RAM 11, first, the address input lines A.sub.1 to A.sub.n of the address bus 20 specify an address in the static RAM 11. Then the levels of the address input lines A.sub.n+1 and A.sub.n+2 are made low. A low-level chip enable signal is input through the chip enable signal line 22. By the above operation, as shown in Table 1, a low-level signal is output from the output terminal T1 of the decoder 21 to the chip select input terminal S of the static RAM 11, and thus the static RAM 11 is selected. Under such conditions, when a low-level write enable signal is input through the write enable line 3 to the write enable input terminal WE of the static RAM 11, data on the data bus 6 is written into an address in the static RAM 11, which address is specified by the address input lines A.sub.1 to A.sub.n.
By changing the levels of the address input lines A.sub.n+1 and A.sub.n+2, in the same manner as described above, data can be written into the static RAMs 12 to 14, which are second, third and fourth static RAMs, respectively. In other words, as can be seen from Table 1, when data is written into the second static RAM 12, the level of the address line A.sub.n+1 is made high, whereas the level of the address line A.sub.n+2 is made low; when data is written into the third static RAM 13, the level of the address line A.sub.n+1 is made low, whereas the level of the address line A.sub.n+2 is made high; and when data is written into the fourth static RAM 14, the respective levels of the address lines A.sub.n+1 and A.sub.n+2 are made high.
However, when the capacity of a memory device, such as that shown in FIG. 7, is expanded by combining a plurality of conventional memory ICs, a decoder separate from the ICs must be provided and connected to the ICs, thus making the circuit wiring complicated, particularly when, e.g., as many as 16 or 32 memory ICs, are combined.
FIG. 8 shows the outward appearance of a conventional memory IC. A semiconductor chip, on which static RAM circuitry as shown in FIG. 6 is formed, is sealed inside a resin package 7. Leads 8 connected to respective electrodes of the semiconductor chip extend from the resin package 7. When a memory device is constructed by mounting a plurality of such memory ICs, in order to reduce the area where the memory ICs are actually mounted on the substrate 9, it is desirable that at least two memory ICs 10a and 10b be mounted one on top of another on the substrate 9, as shown in FIG. 9. At this time, leads which handle signals, such as address input signals common to both of the memory ICs 10a and 10b, come into contact with each other, and are connected electrically. However, as can be seen from FIG. 9, in order to bring the leads of both the memory ICs 10a and 10b into contact with each other on the substrate 9, the shape of the leads of the upper memory IC 10b must differ from the shape of the leads of the lower memory IC 10a. When it is intended to mount a plurality of memory ICs one on top of another, various types of memory ICs of different lead shapes must be manufactured, thus reducing productivity.